1. Field of the Invention
The present invention relates generally to a semi-insulating semiconductor layer having components formed thereon connected by a metal-semiconductor alloy.
2. Description of the Related Art
Devices fabricated using silicon on insulator (SOI) technology are isolated using a shallow trench isolation (STI) process or simply by etching the SOI film that would otherwise connect two active regions of separate devices. The device isolation (e.g. for planar or Fin Field-Effect Transistors (FETs)) is obtained by etching the SOI film down to the buried oxide (BOX). The BOX, however, consists of silicon dioxide (SiO2) which is an insulator, and cannot be transformed into a conductive material to form local wiring.
Semi-insulating (SI) semiconductor compounds, such as a binary compound of InP (indium phosphide), are used widely in radio frequency (RF) circuits as well as opto-electronics (e.g., in laser communication technologies). Indium phosphide is a semiconductor. To turn InP into a semi-insulating (SI) material, the material is doped with impurities such as iron (Fe) or chromium (Cr), which act as traps for free carriers. Of course, semi-insulating semiconductor compounds can be formed in other ways. For example gallium arsenide (GaAs) can be turned semi insulating when bombarded with protons. The semi-insulating (SI) semiconductor compound acts as an insulating structure in the sense that it is voided of free carriers.
Conventionally, interconnects are formed to connect individual devices located on a semi-insulating semiconductor substrate. These conventional interconnects are formed by adding a thick insulating layer over the entire wafer so as to cover the individual semiconductor devices. Holes, or vias, are then formed in the thick insulating layer down to the device terminals (for example the source, drain or gate of a field effect transistor). A metal layer is then formed so as to fill the vias and extend over the thick insulating layer from one individual device to another individual device through the vias so as to connect the individual devices.
The process of connecting the above devices using conventional interconnects adds significant cost to the final device and may limit device density.